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| Am29BL802C Data Sheet The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 22371 Revision C Amendment 7 Issue Date November 3, 2006 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29BL802C 8 Megabit (512 K x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory DISTINCTIVE CHARACTERISTICS 32 words sequential with wrap around (linear 32), bottom boot One 8 Kword, two 4 Kword, one 48 Kword, three 64 Kword, and two 128 Kword sectors Single power supply operation -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors Read access times Burst access times as fast as 17 ns at industrial temperature range (18 ns at extended temperature range) Initial/random access times as fast as 65 ns Alterable burst length via BAA# pin Power dissipation (typical) -- Burst Mode Read: 15 mA @ 25 MHz, 20 mA @ 33 MHz, 25 mA @ 40 MHz -- Program/Erase: 20 mA -- Standby mode, CMOS: 3 A 5 V-tolerant data, address, and control signals Sector Protection -- Implemented using in-system or via programming equipment -- Temporary Sector Unprotect feature allows code changes in previously locked sectors Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses Minimum 100,000 erase cycle guarantee per sector 20-year data retention Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection -- Backward-compatible with AMD Am29LV and Am29F flash memories: powers up in asynchronous mode for system boot, but can immediately be placed into burst mode Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Hardware reset pin (RESET#) -- Hardware method to reset the device for reading array data Package Option -- 56-pin SSOP This Data Sheet states AMD's current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22371 Rev: C Amendment: 7 Issue Date: November 3, 2006 DATA SHEET GENERAL DESCRIPTION The Am29BL802C is an 8 Mbit, 3.0 Volt-only burst mode Flash memory devices organized as 524, 288 words. The device is offered in a 56-pin SSOP package. These devices are designed to be programmed in-system with the standard system 3.0-volt VCC supply. A 12.0-volt VPP or 5.0 VCC is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access times of 65, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Burst Mode Features The Am29BL802C offers a Linear Burst mode--a 32 word sequential burst with wrap around--in a bottom boot configuration only. This devices require additional control pins for burst operations: Load Burst Address (LBA#), Burst Address Advance (BAA#), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. AMD Flash Memory Features Each device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The I/O and control signals are 5V tolerant. The Am29BL802C is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) 2 Am29BL802C 22371C7 November 3, 2006 DATA SHEET TABLE OF CONTENTS This page left intentionally blank. . . . . . . . . . . . . Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 2 4 4 5 6 6 7 8 DQ7: Data# Polling ................................................................. 21 Figure 7. Data# Polling Algorithm .................................................. 21 RY/BY#: Ready/Busy# ............................................................ 22 DQ6: Toggle Bit I .................................................................... 22 DQ2: Toggle Bit II ................................................................... 22 Reading Toggle Bits DQ6/DQ2 ............................................... 22 DQ5: Exceeded Timing Limits ................................................ 23 DQ3: Sector Erase Timer ....................................................... 23 Figure 8. Toggle Bit Algorithm........................................................ 23 Table 5. Write Operation Status ..................................................... 24 Table 1. Device Bus Operations .......................................................8 Requirements for Reading Array Data Array in Asynchronous (Non-Burst) Mode ..................................................................... 9 Requirements for Reading Array Data in Synchronous (Burst) Mode ............................................................................. 9 Burst Suspend/Burst Resume Operations ................................ 9 IND# End of Burst Indicator .................................................... 10 Writing Commands/Command Sequences ............................ 10 Program and Erase Operation Status .................................... 10 Standby Mode ........................................................................ 10 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 10 Output Disable Mode .............................................................. 11 Table 2. Sector Address Table ........................................................11 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25 Figure 9. Maximum Negative Overshoot Waveform ...................... 25 Figure 10. Maximum Positive Overshoot Waveform...................... 25 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .............................................................................. 27 Figure 12. Typical ICC1 vs. Frequency ........................................... 27 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 13. Test Setup..................................................................... 28 Table 6. Test Specifications ........................................................... 28 Key to Switching Waveforms .................................................. 28 Figure 14. Input Waveforms and Measurement Levels ................. 28 Autoselect Mode..................................................................... 12 Table 3. Am29BL802C Autoselect Codes (High Voltage Method) ..12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 15. Conventional Read Operations Timings ....................... Figure 16. Burst Mode Read .......................................................... Figure 17. RESET# Timings .......................................................... Figure 18. Program Operation Timings.......................................... Figure 19. Chip/Sector Erase Operation Timings .......................... Figure 20. Data# Polling Timings (During Embedded Algorithms). Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... Figure 22. DQ2 vs. DQ6 for Erase and Erase Suspend Operations .................................................................... Figure 23. Temporary Sector Unprotect Timing Diagram .............. Figure 24. Sector Protect/Unprotect Timing Diagram .................... Figure 25. Alternate CE# Controlled Write Operation Timings ...... 31 31 32 34 35 36 36 37 37 38 40 Sector Protection/Unprotection ............................................... 12 Figure 1. In-system Sector Protect/Unprotect Algorithms ............... 13 Temporary Sector Unprotect .................................................. 14 Figure 2. Temporary Sector Unprotect Operation........................... 14 Hardware Data Protection . . . . . . . . . . . . . . . . . . 14 Low VCC Write Inhibit .............................................................. 14 Write Pulse "Glitch" Protection ............................................... 14 Logical Inhibit .......................................................................... 14 Power-Up Write Inhibit ............................................................ 14 Command Definitions . . . . . . . . . . . . . . . . . . . . . 14 Reading Array Data in Non-burst Mode ................................. 14 Reading Array Data in Burst Mode ......................................... 15 Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns tIACC, 18 ns tBACC Parameters.................................................................. 15 Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns tIACC, 24 ns tBACC Parameters................................................................. 16 Reset Command ..................................................................... 16 Autoselect Command Sequence ............................................ 16 Program Command Sequence ............................................... 16 Unlock Bypass Command Sequence ..................................... 17 Figure 5. Program Operation .......................................................... 17 Chip Erase Command Sequence ........................................... 17 Sector Erase Command Sequence ........................................ 18 Figure 6. Erase Operation............................................................... 18 Erase Suspend/Erase Resume Commands ........................... 18 Asynchronous Mode ............................................................... 18 Burst Mode ............................................................................. 19 General ................................................................................... 19 Command Definitions ............................................................. 20 Table 4. Am29BL802C Command Definitions ................................20 Erase and Programming Performance . . . . . . . . 41 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 41 SSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 41 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Physical Dimensions*. . . . . . . . . . . . . . . . . . . . . . 42 SSO056--56-Pin Shrink Small Outline Package .................... 42 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision A (June 1, 1999) ...................................................... 43 Revision A+1 (June 25, 1999) ................................................ 43 Revision B (November 29, 1999) ............................................ 43 Revision C (June 20, 2000) .................................................... 43 Revision C+1 (November 16, 2000) ....................................... 43 Revision C+2 (July 22, 2002) ................................................. 43 Revision C+3 (November 22, 2002) ....................................... 43 Revision C+4 (June 4, 2004) .................................................. 44 Revision C+5 (February 28, 2005) ......................................... 44 Revision C+6 (June 29, 2005) ................................................ 44 Revision C7 (November 3, 2006) ........................................... 44 Write Operation Status . . . . . . . . . . . . . . . . . . . . 21 November 3, 2006 22371C7 Am29BL802C 3 DATA SHEET PRODUCT SELECTOR GUIDE Family Part Number Speed Option Regulated Voltage Range: VCC =3.0-3.6 V Temperature Range: Industrial (I), Extended (E) I 65 65 17 18 65R E Am29BL802C 70R I, E 70 70 24 90R I, E 90 90 26 120R I, E 120 120 26 Max access time, ns (tACC) Max CE# access time, ns (tCE) Max burst access time, ns (tBACC) Note: See "AC Characteristics" for full specifications. BLOCK DIAGRAM DQ0-DQ15 RY/BY# VCC VSS Sector Switches Input/Output Buffers Erase Voltage Generator WE# State Control Command Register CE# OE# PGM Voltage Generator IND# Buffer IND# RESET# Chip Enable Output Enable Logic A3, A4 STB Data Latch VCC Detector Timer STB Address Latch Y-Decoder Y-Gating A0-A18 X-Decoder Cell Matrix A0-A4 LBA# BAA# CLK Burst State Counter Burst Address Counter A3, A4 A0-A2 4 Am29BL802C 22371C7 November 3, 2006 A0-A2 DATA SHEET CONNECTION DIAGRAMS WE# RESET# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# NC VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VSS CLK BAA# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 LBA# VCC NC NC A8 A9 A10 A11 A12 A13 A14 A15 A16 NC NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC VCC IND# NC 56-Pin SSOP November 3, 2006 22371C7 Am29BL802C 5 DATA SHEET BAA# Low enables the burst mode Flash device to read from the next word when gated with the rising edge of the clock. Data becomes available tBACC ns of burst access time after the rising edge of the clock BAA # High prevents the rising edge of the clock from advancing the data to the next word output. The output data remains unchanged. IND# = Highest burst counter address reached. IND# is low at the end of a 32-word burst sequence (when word Da + 31 is output). The output will wrap around to Da on the next CLK cycle (with BAA# low). Hardware reset input PIN CONFIGURATION A0-A18 = 19 addresses 16 data inputs/outputs Chip Enable Input. This signal shall be asynchronous relative to CLK for the burst mode. Output Enable Input. This signal shall be asynchronous relative to CLK for the burst mode. Write enable. This signal shall be asynchronous relative to CLK for the burst mode. Device ground No connect. Pin not connected internally Ready Busy output Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. CLK latches input addresses in conjunction with LBA# input and increments the burst address with the BAA# input. Load Burst Address input. Indicates that the valid address is present on the address inputs. LBA# Low at the rising edge of the clock latches the address on the address inputs into the burst mode Flash device. Data becomes available tPACC ns of initial access time after the rising edge of the same clock that latches the address. LBA# High indicates that the address is not valid BAA# = Burst Address Advance input. Increments the address during the burst mode operation RESET# = DQ0-DQ15 = CE# = OE# = WE# = VSS NC RY/BY# CLK = = = = Note: The address, data, and control signals (RY/BY#, LBA, BAA, IND, RESET, OE#, CE#, and WE#) are 5 V tolerant. LOGIC SYMBOL 19 A0-A18 DQ0-DQ15 CLK CE# OE# WE# RESET# LBA# BAA# RY/BY# IND# 16 LBA# = 6 Am29BL802C 22371C7 November 3, 2006 DATA SHEET ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29BL802C B 65R Z I TEMPERATURE RANGE I = Industrial (-40C to +85C) E = Extended (-40C to +125C) F = Industrial (-40C to +85C) for Pb-free Package K = Extended (-40C to +125C) for Pb-free Package PACKAGE TYPE Z = 56-Pin Shrink Small Outline Package (SSO056) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29BL802C 8 Megabit (512 K x 16-Bit) CMOS High Performance Burst Mode Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations Am29BL802CB-65R Am29BL802CB-70R Am29BL802CB-90R Am29BL802CB-120R ZI, ZE, ZF, ZK ZI, ZE, ZF, ZK ZI, ZE, ZF, ZK ZI, ZE, ZF, ZK Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. For information on full voltage range options (2.7-3.6 V), please contact AMD. November 3, 2006 22371C7 Am29BL802C 7 DATA SHEET DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Operation Read Write Standby Output Disable Reset Sector Protect (Note 2) CE# L L VCC 0.3 V L X L Device Bus Operations CLK X X X X X X LBA# BAA# X X X X X X X X X X X X Addresses (Note 1) AIN AIN X HIGH Z X Sector Address, A6 = L, A1 = H, A0 = L Sector Address, A6 = H, A1 = H, A0 = L AIN Data (DQ0-DQ15) DOUT DIN HIGH Z HIGH Z HIGH Z DIN OE# WE# RESET# L H X H X H H L X H X L H H VCC 0.3 V H L VID Sector Unprotect (Note 2) Temporary Sector Unprotect Burst Read Operations Load Starting Burst Address Advance burst to Next address (no data presented on the data bus Advance burst to Next address (appropriate data presented on the data bus Terminate Current burst Read Cycle Terminate Current burst Read Cycle; Start New Burst Read Cycle Burst Suspend: (All data is retained internally in the device) Burst Resume: (Same data as Burst suspend) Burst Resume: (Incremented data from Burst Suspend) Legend: L X H X L X VID VID X X X X X X DIN HIGH Z L L X H H H H H L H H L AIN X X HIGH Z Data Out DQ0-DQ15 HIGH Z X HIGH Z Data Out DQ0-DQ15 Data Out DQ0-DQ15 L H L L L L L X X H L L H H H H H H H H H H H H X H X L H H H L X H H H L X X AIN X X X L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. Notes: 1. Addresses are A18:A0. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Protection/Unprotection" section. 8 Am29BL802C 22371C7 November 3, 2006 DATA SHEET the device. The first burst data is available after the initial access time (tIACC) from the rising edge of the CLK that loads the burst address. After the initial access, subsequent burst data is available tBACC after each rising edge of CLK. The device increments the address at each rising edge of the clock cycles while BAA# is asserted low. The 5bit burst address counter is set to 00000b at the starting address. When the burst address counter is reaches 11111b, the device outputs the last word in the burst sequence, and outputs a low on IND#. If the system continues to assert BAA#, on the next CLK the device will output the data for the starting address--the burst address counter will have "wrapped around" to 00000b. For example, if the initial address is xxxx0h, the data order will be 0-1-2-3.....28-29-30-31-0-1...; if the initial address is xxxx2h, the data order will be 2-34-5.....28-29-30-31-0-1-2-3...; if the initial address is xxxx8h, the data order will be 8-9-10-11.....30-31-0-12-3-4-5-6-7-8-9....; and so on. Data will be repeated if more than 32 clocks are supplied, and BAA# remains asserted low. A burst mode read operation is terminated using one of three methods: -- In the first method, CE# is asserted high. The device in this case remains in burst mode; asserting LBA# low terminates the previous burst read cycle and starts a new burst read cycle with the address that is currently valid. -- In the second method, the Burst Disable command sequence is written to the device. The device halts the burst operation and returns to the asynchronous mode. -- In the third method, RESET# is asserted low. All opertations are immediately terminated, and the device will revert to the asynchronous mode. Note that writing the reset command will not terminate the burst mode. Requirements for Reading Array Data Array in Asynchronous (Non-Burst) Mode To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t C E ) is the delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least tACC-tOE time). The internal state machine is set for reading array data in the upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data in Non-burst Mode" for more information. Refer to the AC Read Operations table for timing specifications and to Figure 15 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Requirements for Reading Array Data in Synchronous (Burst) Mode The device offers fast 32-word sequential burst reads and is used to support microprocessors that implement an instruction prefetch queue, as well as large data transfers during system configuration. Three additional pins--Load Burst Address (LBA#), Burst Address Advance (BAA#), and Clock (CLK)-- allow interfacing to microprocessors and microcontrollers with minimal glue logic. Burst mode read is a synchronous operation tied to the rising edge of CLK. CE#, OE#, and WE# are asynchronous (relative to CLK). When the device is in asynchronous mode (after power-up or RESET# pulse), any signals on the CLK, LBA#, and BAA# inputs are ignored. The device operates as a conventional flash device, as described in the previous section. To enable burst mode operation, the system must issue the Burst Mode Enable command sequence (see Table 4). After the device has entered the burst mode, the system must assert Load Burst Address (LBA#) low for one clock period, which loads the starting address into Burst Suspend/Burst Resume Operations The device offers Burst Suspend and Burst Resume operations. When both OE# and BAA# are taken high, the device removes ("suspends") the data from the outputs (because OE# is high), but "holds" the data internally. The device resumes burst operation when either OE# and/or BAA# is asserted low. Asserting the OE# only causes the device to present the same data that was held during the Burst Suspend operation. As long as BAA# is high, the device will continue to output that word of data. Asserting both OE# and BAA# low resumes the burst operation, and on the next rising edge of CLK, increments the counter and outputs the next word of data. November 3, 2006 22371C7 Am29BL802C 9 DATA SHEET outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification. IND# End of Burst Indicator The IND# output signal goes low when the device is ouputting the last word of a 32-word burst sequence (word Da+31). When the starting address was loaded with LBA#, the 5-bit burst address counter was set to 00000b. The counter increments to 11111b on the 32nd word in the burst sequence. If the system continues to assert BAA# low, on the next CLK the device will output the starting address data (Da). The burst address counter will be again set to 00000b, and will have "wrapped around." Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The "Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a pro22371C7 November 3, 2006 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to "AC Characteristics" for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the 10 Am29BL802C DATA gram or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 17 for the timing diagram. SHEET Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 A18 0 0 0 0 0 0 0 1 1 A17 0 0 0 0 0 1 1 0 1 A16 0 0 0 0 1 0 1 X X X X X X X A15 0 0 0 01, 11 X X X X X A14 0 0 0 Sector Address Table A13 0 1 1 X X X X X X A12 X 0 1 X X X X X X Sector Size 8 Kwords 4 Kwords 4 Kwords 48 Kwords 64 Kwords 64 Kwords 64 Kwords 128 Kwords 128 Kwords Address Range 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-5FFFFh 60000h-7FFFFh November 3, 2006 22371C7 Am29BL802C 11 DATA SHEET Table 1. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 1 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 4. This method does not require VID. See "Command Definitions" for details on using the autoselect mode. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 3. Am29BL802C Autoselect Codes (High Voltage Method) A18 A11 to to WE# A12 A10 H H X X X X A8 to A7 X X A5 to A2 X X DQ7 to DQ0 0001h 0081h 0001h (protected) Sector Protection Verification L L H SA X VID X L X H L 0000h (unprotected) 0000h (non-burst mode) 0001h (burst mode) Description Manufacturer ID: AMD Device ID: Am29BL802CB (Bottom Boot Block) CE# L L OE# L L A9 VID VID A6 L L A1 L L A0 L H Burst Mode Status L L H X X VID X L X H H L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences. See Table 4. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Details on this method are provided in a supplement, publication number 22372, available on www.spansion.com. 12 Am29BL802C 22371C7 November 3, 2006 DATA SHEET START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 s Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Increment PLSCNT Reset PLSCNT = 1 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 1. In-system Sector Protect/Unprotect Algorithms November 3, 2006 22371C7 Am29BL802C 13 DATA SHEET Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. HARDWARE DATA PROTECTION The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 4 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit START RESET# = VID (Note 1) Perform Erase or Program Operations When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. RESET# = VIH Logical Inhibit Temporary Sector Unprotect Completed (Note 2) Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Figure 2. Temporary Sector Unprotect Operation COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 4 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, Reading Array Data in Non-burst Mode The device is automatically set to reading array data after device power-up. No commands are required to 14 Am29BL802C 22371C7 November 3, 2006 DATA or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data Array in Asynchronous (Non-Burst) Mode" in the "Key to Switching Waveforms" section for more information. The Read Operations table provides the read parameters, and Figure 15 shows the timing diagram. SHEET least the next rising edge of the CLK signal, upon which the device loads the initial burst address. 2. The system returns LBA# to a logic high. The device requires that the next rising edge of CLK occur with LBA# high for proper burst mode operation. Typically, the initial number of CLK cycles depends on the clock frequency and the rated speed of the device. 3. After the initial data has been read, the system asserts BAA# low to indicate it is ready to read the remaining burst read cycles. Each successive rising edge of the CLK signal then causes the flash device to increment the burst address and output sequential burst data. 4. When the device outputs the last word of data in the 32-word burst mode read sequence, the device outputs a logic low on the IND# pin. This indicates to the system that the burst mode read sequence is complete. 5. To exit the burst mode, the system must write the four-cycle Burst Mode Disable command sequence. The device will also exit the burst mode if powered down or if RESET# is asserted. The device will not exit the burst mode if the reset command is written. Reading Array Data in Burst Mode The device powers up in the non-burst mode. To read array data in burst mode, the system must write the four-cycle Burst Mode Enable command sequence (see Table 4). The device then enters burst mode. In addition to asserting CE#, OE#, and WE# control signals, burst mode operation requires that the system provide appropriate LBA#, BAA#, and CLK signals. For successful burst mode reads, the following events must occur (refer to Figures 3 and 4 for this discussion): 1. The system asserts LBA# low, indicating to the device that a valid initial burst address is available on the address bus. LBA# must be kept low until at Step 1 25 ns CLK LBA# BAA# Step 2 25 ns 25 ns Step 3 25 ns 25 ns Da Da +1 Da +2 Data 65 ns OE# 18 ns 18 ns Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns tIACC, 18 ns tBACC Parameters November 3, 2006 22371C7 Am29BL802C 15 DATA SHEET Step 1 40 ns CLK LBA# BAA# Step 2 40 ns Step 3 40 ns 40 ns 40 ns Da Da +1 Da +2 Da +3 Data 70 ns 24 ns 24 ns 24 ns OE# Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns tIACC, 24 ns tBACC Parameters Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). See "AC Characteristics" for parameters, and to Figure 17 for the timing diagram. is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address 00h retrieves the manufacturer code. A read cycle at address 01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode returns 0001h if that sector is protected, or 0000h if it is unprotected. Refer to Table 2 for valid sector addresses. A read cycle at address 03h returns 0000h if the device is in asynchronous mode, or 0001h if in synchronous (burst) mode. The system must write the reset command to exit the autoselect mode and return to reading array data. Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 4 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See "Write Operation Status" for information on these status bits. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 4 shows the address and data requirements. This method is an alternative to that shown in Table 1, which 16 Am29BL802C 22371C7 November 3, 2006 DATA Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1," or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 4 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't care for both cycles. The device then returns to reading array data. Figure 5 illustrates the algorithm for the program operation. See the Erase/Program Operations table in "AC Characteristics" for parameters, and to Figure 18 for timing diagrams. SHEET START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 4 for program command sequence. Figure 5. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 4 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. November 3, 2006 22371C7 Am29BL802C 17 DATA The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 6 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 19 for timing diagrams. SHEET When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to "Write Operation Status" for information on these status bits.) Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to Figure 19 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 4 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. No START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. See Table 4 for erase command sequence. 2. See "DQ3: Sector Erase Timer" for more information. Figure 6. Erase Operation Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The Erase Suspend command has a different effect depending on whether the Flash device is in Asynchronous Mode or Burst Mode. Asynchronous Mode The Erase Suspend command is only valid when the Flash device is in Asynchronous Mode. During Erase Suspend operation Asynchronous read/program operations behave normally in non-erasing sectors. However, Erase Suspend operation prevents the Flash 18 Am29BL802C 22371C7 November 3, 2006 DATA device from entering Burst Mode. To enter Burst Mode either the Erase operation must be allowed to complete normally, or it can be prematurely terminated by issuing a Hardware Reset. Burst Mode While in Burst Mode the Erase Suspend command is ignored and the device continues to operate normally in Burst Mode. If Erase Suspend operation is required, then Burst Mode must be terminated and Asynchronous Mode initiated. General This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal SHEET read and write timings and command definitions apply. Note that burst read is not available when the device is erase-suspended. Only asynchronous reads are allowed. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. November 3, 2006 22371C7 Am29BL802C 19 DATA SHEET Command Definitions Table 4. Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Manufacturer ID Device ID, Bottom Boot Block Cycles Am29BL802C Command Definitions Second Addr Data Bus Cycles (Notes 2-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data Autoselect (Note 8) 1 1 4 4 4 4 4 3 2 2 6 6 1 1 4 4 First Addr Data RA RD XXX F0 555 AA 555 AA 555 555 555 555 XXX XXX 555 555 XXX XXX 555 555 AA AA AA AA A0 90 AA AA B0 30 AA AA 2AA 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 55 55 55 PD 00 55 55 555 555 555 555 555 555 90 90 90 90 A0 20 X00 X01 (SA) X02 X03 PA Sector Protect Verify (Note 9) Burst Mode Status (Note 10) Program Unlock Bypass Unlock Bypass Program (Note 11) Unlock Bypass Reset (Note 12) Chip Erase Sector Erase Erase Suspend (Note 13) Erase Resume (Note 14) Burst Mode Burst Mode Enable Burst Mode Disable 01 2281 0000 0001 0000 0001 PD 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 2AA 2AA 55 55 555 555 C0 C0 XXX XXX 01 00 Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 5. Address bits A18-A11 are don't cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. 10. The data is 00h if the device is in asynchronous mode and 01h if in synchronous (burst) mode. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 14. The Erase Resume command is valid only during the Erase Suspend mode. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18-A12 uniquely select any sector. 20 Am29BL802C 22371C7 November 3, 2006 DATA SHEET WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 5 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 5 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algorithm. START DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7- DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 20, Data# Polling Timings (During Embedded Algorithms), in the "AC Characteristics" section illustrates this. Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 7. Data# Polling Algorithm November 3, 2006 22371C7 Am29BL802C 21 DATA SHEET Table 5 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. Figure 21 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on "DQ2: Toggle Bit II". RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 5 shows the outputs for RY/BY#. Figures 15, 17, 18 and 19 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 5 to compare outputs for DQ2 and DQ6. Figure 8 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on "DQ7: Data# Polling"). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Reading Toggle Bits DQ6/DQ2 Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system 22371C7 November 3, 2006 22 Am29BL802C DATA must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8). SHEET START Read Byte (DQ0-DQ7) Address = VA Read Byte (DQ0-DQ7) Address = VA (Note 1) DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice (DQ 0-DQ7) Adrdess = VA (Notes 1, 2) DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 5 shows the outputs for DQ3. DQ6 = Toggle? No Yes FAIL PASS Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text. Figure 8. Toggle Bit Algorithm November 3, 2006 22371C7 Am29BL802C 23 DATA SHEET Table 5. Write Operation Status Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeded Timing Limits" for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 24 Am29BL802C 22371C7 November 3, 2006 DATA SHEET ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . -0.5 V to +13.0 V All other pins (Note 1). . . . . . . . . . . -0.5 V to +5.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input and I/O pins is -0.5 V. During voltage transitions, input and I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on output and I/Os is VCC + 0.5 V. During voltage transitions input and I/Os may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 10. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9 and OE# is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. 3. 3.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. 4.Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns +0.8 V -0.5 V -2.0 V 20 ns 20 ns Figure 9. Maximum Negative Overshoot Waveform 20 ns Figure 10. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . -40C to +125C VCC Supply Voltages VCC for regulated voltage range. . . . . . . 3.0 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. November 3, 2006 22371C7 Am29BL802C 25 DATA SHEET DC CHARACTERISTICS CMOS Compatible Parameter ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 ICC5 Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Read Current (Notes 1, 2) VCC Active Write Current (Notes 2, 3, 6) VCC Standby Current (Note 2) VCC Standby Current During Reset (Note 2) Automatic Sleep Mode (Notes 2, 4) Test Conditions VIN = VSS to 5.5 V, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to 5.5 V, VCC = VCC max CE# = VIL, OE# = VIH, 5 MHz CE# = VIL, OE# = VIH CE#, RESET# = VCC0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V OE# = VIH OE# = VIL 25 MHz ICC6 VCC Burst Mode Read Current (Notes 2, 5) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 4) VCC = 3.3 V IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 0.85 x VCC VCC-0.4 2.3 2.5 V CE# = VIL, OE# = VIH 33 MHz 40 MHz VIL VIH VID VOL VOH1 VOH2 VLKO -0.5 0.7 x VCC 11.5 9 20 3 3 3 8 15 20 25 Min Typ Max 1.0 35 1.0 16 30 10 10 10 20 30 35 40 0.8 5.5 12.5 0.45 Unit A A A mA mA A A A A mA mA mA V V V V V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 3 A. 5. 32-word average. 6. Not 100% tested. 26 Am29BL802C 22371C7 November 3, 2006 DATA SHEET DC CHARACTERISTICS (Continued) Zero Power Flash 25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000 Note: Addresses are switching at 1 MHz Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 10 3.6 V 8 Supply Current in mA 2.7 V 6 4 2 0 1 2 3 Frequency in MHz Note: T = 25 C 4 5 Figure 12. Typical ICC1 vs. Frequency November 3, 2006 22371C7 Am29BL802C 27 DATA SHEET TEST CONDITIONS Table 6. 3.3 V Test Condition Device Under Test CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Note: Diodes are IN3064 or equivalent 5 0.0-3.0 1.5 1.5 ns V V V 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) 30 65R, 70R 90R, 120R 1 TTL gate 100 pF Unit Test Specifications Figure 13. Test Setup Output timing measurement reference levels Key to Switching Waveforms WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS 3.0 V 0.0 V Input 1.5 V Measurement Level 1.5 V Output Figure 14. Input Waveforms and Measurement Levels 28 Am29BL802C 22371C7 November 3, 2006 DATA SHEET AC CHARACTERISTICS Read Operations Parameter 65R JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std. Description tRC Read Cycle Time (Note 1) Test Setup Min CE# = VIL Max OE# = VIL OE# = VIL Max Max Max Max Min Min Min 17 17 20 I 65 65 65 18 18 E Speed Options and Temperature Ranges 70R I, E 70 70 70 24 24 25 0 10 0 90R I, E 90 90 90 26 26 30 120R I, E 120 120 120 26 26 30 Unit ns ns ns ns ns ns ns ns ns tACC Address to Output Delay tCE tOE tDF tDF Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Read Output Enable tOEH Hold Time (Note 1) Toggle and Data# Polling tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Notes: 1. Not 100% tested. 2. See Figure 13 and Table 6 for test specifications November 3, 2006 22371C7 Am29BL802C 29 DATA SHEET AC CHARACTERISTICS Burst Mode Read Parameter Speed Options and Temperature Ranges 65R JEDEC Std. tIACC Description Initial Access Time LBA# Valid Clock to Output Delay (See Note) Burst Access Time BAA# Valid Clock to Output Delay LBA# Setup Time LBA# Hold Time BAA# Setup Time BAA# Hold Time Data Hold Time from Next Clock Cycle Address Setup Time to CLK (See Note) Address Hold Time from CLK (See Note) Output Enable to Output Valid Output Enable to Output High Z Chip Enable to Output High Z CE# Setup Time to Clock Max 65 70 90 120 ns I E 70R I, E 90R I, E 120R I, E Unit tBACC tLBAS tLBAH tBAAS tBAAH tBDH tACS tACH tOE tOEZ tCEZ tCES Max Min Min Min Min Max Min Min Max Max Min Min 17 18 24 6 2 6 2 4 6 2 26 26 ns ns ns ns ns ns ns ns 17 20 20 18 24 25 25 6 26 30 30 26 30 30 ns ns ns ns Note: Initial valid data will be output after second clock rising edge of LBA# assertion. 30 Am29BL802C 22371C7 November 3, 2006 DATA SHEET AC CHARACTERISTICS tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC OE# 0V Figure 15. Conventional Read Operations Timings tCES CE# CLK tLBAS LBA# tLBAH BAA# A0: A18 tACS Aa tCEZ tBAAS tBAAH tBDH tBACC Da Da + 1 Da + 2 Da + 3 Da + 31 tACH DQ0: DQ15 tIACC OE#* tOE tOEZ IND# Figure 16. Burst Mode Read November 3, 2006 22371C7 Am29BL802C 31 DATA SHEET AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Test Setup Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 17. RESET# Timings 32 Am29BL802C 22371C7 November 3, 2006 DATA SHEET AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min Min Max 35 35 30 9 1 50 0 90 45 35 45 35 0 0 0 0 0 35 50 65R 65 Speed Options 70R 70 0 45 45 50 50 90R 90 120R 120 Unit ns ns ns ns ns ns ns ns ns ns ns s sec s ns ns tWHWH1 Programming Operation (Note 2) tWHWH2 Sector Erase Operation (Note 2) tVCS tRB tBUSY VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. November 3, 2006 22371C7 Am29BL802C 33 DATA SHEET AC CHARACTERISTICS Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles) tCH A0h VCC tVCS Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 18. Program Operation Timings 34 Am29BL802C 22371C7 November 3, 2006 DATA SHEET AC CHARACTERISTICS Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 tDH Data 55h 30h 10 for Chip Erase In Progress Complete tBUSY RY/BY# tVCS VCC tRB Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). Figure 19. Chip/Sector Erase Operation Timings November 3, 2006 22371C7 Am29BL802C 35 DATA SHEET AC CHARACTERISTICS tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ0-DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY# High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. Toggle Bit Timings (During Embedded Algorithms) 36 Am29BL802C 22371C7 November 3, 2006 DATA SHEET AC CHARACTERISTICS Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 22. DQ2 vs. DQ6 for Erase and Erase Suspend Operations Temporary Sector Unprotect Parameter JEDEC Std. tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s Note: Not 100% tested. 12 V RESET# 0 or 3 V tVIDR Program or Erase Command Sequence CE# tVIDR WE# tRSP RY/BY# Figure 23. Temporary Sector Unprotect Timing Diagram November 3, 2006 22371C7 Am29BL802C 37 DATA SHEET AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h Sector Protect: 150 s Sector Unprotect: 15 ms Valid* Data 1 s CE# 60h 60h Status WE# OE# Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 24. Sector Protect/Unprotect Timing Diagram 38 Am29BL802C 22371C7 November 3, 2006 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std tWC tAS tAH tDS tDH tOES tGHEL tWLEL tEHWH tELEH tEHEL tWHWsH1 tWHWH2 tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Min Min Min Min Min Min Min Min Min Min Min Typ Typ 35 35 30 9 1 45 35 45 35 0 0 0 0 0 35 50 65R 65 Speed Options 70R 70 0 45 45 50 50 90R 90 120R 120 Unit ns ns ns ns ns ns ns ns ns ns ns s sec tWHWH1 Programming Operation (Note 2) tWHWH2 Sector Erase Operation (Note 2) Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. November 3, 2006 22371C7 Am29BL802C 39 DATA SHEET AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. Figure 25. Alternate CE# Controlled Write Operation Timings 40 Am29BL802C 22371C7 November 3, 2006 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Programming Time Chip Programming Time (Note 3) Typ (Note 1) 5 45 9 9 360 27 Max (Note 2) 15 Unit s s s s Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 3.0 V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 4 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1 million cycles. LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA SSOP PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. DATA RETENTION Parameter Minimum Pattern Data Retention Time 125C * For reference only. BSC is an ANSI standard for Basic Space Centering. 20 Years Test Conditions 150C Min 10 Unit Years November 3, 2006 22371C7 Am29BL802C 41 DATA SHEET PHYSICAL DIMENSIONS* SSO056--56-Pin Shrink Small Outline Package Dwg rev AB; 10/99 42 Am29BL802C 22371C7 November 3, 2006 DATA SHEET REVISION SUMMARY Revision A (June 1, 1999) Initial release. Burst Mode Read with 40 MHz CLK figure Changed tBACC for the 65R speed option in the industrial temperature range from 19 to 18 ns. Read Operations table Changed tOE and tDF for the 65R speed option in the industrial temperature range from 19 to 18 ns. Burst Mode Read table Changed tOE and tBACC for the 65R speed option in the industrial temperature range from 19 to 18 ns. Burst Mode Read figure Corrected BAA# waveform to return high before the final clock cycle shown. Erase and Programming Performance table, Erase and Program Operations table, Alternate CE# Controlled Erase and Program Operations table Resolved differences in typical sector erase times. The typical sector erase time for all sectors is 3 sec. Revision A+1 (June 25, 1999) General Description Corrected the device density in the first paragraph. Command Definitions Reading Array Data in Burst Mode: Added reference to Figure 3 in the first paragraph. Revision B (November 29, 1999) Global All speed options are now offered only at the regulated voltage range of 3.0 to 3.6 V. The 90 and 120 speed options now have a tOE of 26 ns at the industrial temperature range. The 70 ns speed option is now available at the extended temperature range. AC Characteristics In Figures 17 and 18, deleted tGHWL; modified OE# waveform. Physical Dimensions Updated drawing of SSOP to new version. Revision C+1 (November 16, 2000) Global Deleted Preliminary status from document. Added table of contents. Added Figure 1, In-system Sector Protect/Unprotect Algorithms figure to document (was missing from previous revisions). Revision C (June 20, 2000) Global The "advance information" data sheet designation has been changed to "preliminary." Only minor parameter changes, if any, may occur. Speed, package, and temperature range combinations may also change in future data sheet revisions. Distinctive Characteristics Changed burst access time specification for the 65R speed option in the industrial temperature range from 19 to 18 ns. Product Selector Guide Replaced tOE with tBACC to more clearly distinguish burst mode access from asynchronous access times. Note however, that in burst mode, tOE and tBACC specifications are identical. Changed t BACC for the 65R speed option in the industrial temperature range from 19 to 18 ns. Ordering Information Burn-in processing is no longer available. Requirements for Reading Array Data Array in Asynchronous (Non-Burst) Mode Clarified the description of how to terminate a burst mode read operation. Revision C+2 (July 22, 2002) Pin Description, IND# End of Burst Indicator Clarified description of IND# function. Table 1, Device Bus Operations In burst read operations section, changed BAA# to "H" for "Load starting Burst Address" and Terminate Current Burst Read Cycle; Start New Burst Read Cycle." Requirements for Reading Array Data in Synchronous (Burst) Mode Modified section to clarify the description of the IND# and burst read functions. Burst Sequence Table Deleted table. Revision C+3 (November 22, 2002) Distinctive Characteristics Changed endurance to 1 million cycles. Erase Suspend/Erase Resume Command Sequence Noted that only asynchronous reads are allowed during the erase suspend mode, added asynchronous mode and burst mode section. November 3, 2006 22371C7 Am29BL802C 43 DATA Erase/Program Operations table, Alternate CE# Controlled Erase/Program Operations table Changed typical sector erase time from 3 s to 1 s. Erase and Programming Performance Changed typical/maximum sector erase time from 3 s/60 s to 5 s/15 s, respectively. Changed typical chip erase time from 22 s to 45 s. Changed endurance to 1 million cycles. SHEET Valid Combinations Table Added Pb-free combinations. Revision C+6 (June 29, 2005) Distinctive Characteristics Changed bullet point value from 1,000,000 to 100,000. Erase and Programming Performance Changed values for "Sector Erase Time" and "Chip Erase Time" parameters. Adjusted notes values from 1,000,000 to 100,000. Ordering Information Changed Extended temperature range to -40C. Revision C+4 (June 4, 2004) Ordering Information Changed Extended temperature range to -40C. Operating Ranges Changed Extended temperature range to -40C. Revision C7 (November 3, 2006) Sector Protection/Unprotection Corrected reference to programming supplement publication number and location. Erase and Program Operations table Changed tBUSY to a maximum specification. Revision C+5 (February 28, 2005) Ordering Information Changed Extended temperature range to -55C. Added Pb-free package information. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright (c) 1999-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright (c) 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 44 Am29BL802C 22371C7 November 3, 2006 |
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